Merge pull request #1814 from YosysHQ/mmicko/pyosys_makefile
[yosys.git] / tests / simple / attrib04_net_var.v
1 module bar(clk, rst, inp, out);
2 input wire clk;
3 input wire rst;
4 input wire inp;
5 output reg out;
6
7 (* this_is_a_prescaler *)
8 reg [7:0] counter;
9
10 (* temp_wire *)
11 wire out_val;
12
13 always @(posedge clk)
14 counter <= counter + 1;
15
16 assign out_val = inp ^ counter[4];
17
18 always @(posedge clk)
19 if (rst) out <= 1'd0;
20 else out <= out_val;
21
22 endmodule
23
24 module foo(clk, rst, inp, out);
25 input wire clk;
26 input wire rst;
27 input wire inp;
28 output wire out;
29
30 bar bar_instance (clk, rst, inp, out);
31 endmodule
32