tests/simple/attrib06_operator_suffix.v

   1 module bar(clk, rst, inp_a, inp_b, out);
   2   input  wire clk;
   3   input  wire rst;
   4   input  wire [7:0] inp_a;
   5   input  wire [7:0] inp_b;
   6   output reg  [7:0] out;
   7
   8   always @(posedge clk)
   9     if (rst) out <= 0;
  10     else     out <= inp_a + (* ripple_adder *) inp_b;
  11
  12 endmodule
  13
  14 module foo(clk, rst, inp_a, inp_b, out);
  15   input  wire clk;
  16   input  wire rst;
  17   input  wire [7:0] inp_a;
  18   input  wire [7:0] inp_b;
  19   output wire [7:0] out;
  20
  21   bar bar_instance (clk, rst, inp_a, inp_b, out);
  22 endmodule
  23