Merge pull request #1814 from YosysHQ/mmicko/pyosys_makefile
[yosys.git] / tests / simple / attrib09_case.v
1 module bar(clk, rst, inp, out);
2 input wire clk;
3 input wire rst;
4 input wire [1:0] inp;
5 output reg [1:0] out;
6
7 always @(inp)
8 (* full_case, parallel_case *)
9 case(inp)
10 2'd0: out <= 2'd3;
11 2'd1: out <= 2'd2;
12 2'd2: out <= 2'd1;
13 2'd3: out <= 2'd0;
14 endcase
15
16 endmodule
17
18 module foo(clk, rst, inp, out);
19 input wire clk;
20 input wire rst;
21 input wire [1:0] inp;
22 output wire [1:0] out;
23
24 bar bar_instance (clk, rst, inp, out);
25 endmodule
26