tests/simple/carryadd.v

   1 module carryadd(a, b, y);
   2
   3 parameter WIDTH = 8;
   4
   5 input [WIDTH-1:0] a, b;
   6 output [WIDTH-1:0] y;
   7
   8 genvar i;
   9 generate
  10         for (i = 0; i < WIDTH; i = i+1) begin:STAGE
  11                 wire IN1 = a[i], IN2 = b[i];
  12                 wire C, Y;
  13                 if (i == 0)
  14                         assign C = IN1 & IN2, Y = IN1 ^ IN2;
  15                 else
  16                         assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C),
  17                                Y = IN1 ^ IN2 ^ STAGE[i-1].C;
  18                 assign y[i] = Y;
  19         end
  20 endgenerate
  21
  22 // assert property (y == a + b);
  23
  24 endmodule