tests/simple/defvalue.sv

   1 module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
   2         cnt #(1) foo (.clock, .cnt(cnt1), .delta);
   3         cnt #(2) bar (.clock, .cnt(cnt2));
   4 endmodule
   5
   6 module cnt #(
   7         parameter integer initval = 0
   8 ) (
   9         input clock,
  10         output logic [3:0] cnt = initval,
  11 `ifdef __ICARUS__
  12         input [3:0] delta
  13 `else
  14         input [3:0] delta = 10
  15 `endif
  16 );
  17 `ifdef __ICARUS__
  18         assign (weak0, weak1) delta = 10;
  19 `endif
  20         always @(posedge clock)
  21                 cnt <= cnt + delta;
  22 endmodule