9 module dffa(clk, arst, d, q);
12 always @(posedge clk or posedge arst) begin
20 module dffa1(clk, arst, d, q);
23 always @(posedge clk or negedge arst) begin
31 module dffa2(clk, arst, d, q);
34 always @(posedge clk or negedge arst) begin
42 module dffa3(clk, arst, d, q);
45 always @(posedge clk or negedge arst) begin
53 module dffa4(clk, arst1, arst2, arst3, d, q);
54 input clk, arst1, arst2, arst3, d;
56 always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
68 // SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of
69 // simulation-implementation mismatches. The following testcases try to cover the
70 // part that is defined and avoid the undefined cases.
72 module dffsr1(clk, arst, d, q);
75 always @(posedge clk, posedge arst) begin
77 q <= d^d; // constant expression -- but the frontend optimizer does not know that..
83 module dffsr2(clk, preset, clear, d, q);
84 input clk, preset, clear, d;
87 wire clk, preset, clear, d;
88 dffsr2_sub uut (clk, preset && !clear, !preset && clear, d, q);
92 module dffsr2_sub(clk, preset, clear, d, q);
93 input clk, preset, clear, d;
95 always @(posedge clk, posedge preset, posedge clear) begin