tests/simple/dff_different_styles.v

   1
   2 module dff(clk, d, q);
   3 input clk, d;
   4 output reg q;
   5 always @(posedge clk)
   6         q <= d;
   7 endmodule
   8
   9 module dffa(clk, arst, d, q);
  10 input clk, arst, d;
  11 output reg q;
  12 always @(posedge clk or posedge arst) begin
  13         if (arst)
  14                 q <= 1;
  15         else
  16                 q <= d;
  17 end
  18 endmodule
  19
  20 module dffa1(clk, arst, d, q);
  21 input clk, arst, d;
  22 output reg q;
  23 always @(posedge clk or negedge arst) begin
  24         if (~arst)
  25                 q <= 0;
  26         else
  27                 q <= d;
  28 end
  29 endmodule
  30
  31 module dffa2(clk, arst, d, q);
  32 input clk, arst, d;
  33 output reg q;
  34 always @(posedge clk or negedge arst) begin
  35         if (!arst)
  36                 q <= 0;
  37         else
  38                 q <= d;
  39 end
  40 endmodule
  41
  42 module dffa3(clk, arst, d, q);
  43 input clk, arst, d;
  44 output reg q;
  45 always @(posedge clk or negedge arst) begin
  46         if (~(!arst))
  47                 q <= d;
  48         else
  49                 q <= 1;
  50 end
  51 endmodule
  52
  53 module dffa4(clk, arst1, arst2, arst3, d, q);
  54 input clk, arst1, arst2, arst3, d;
  55 output reg q;
  56 always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
  57         if (arst1)
  58                 q <= 0;
  59         else if (arst2)
  60                 q <= 0;
  61         else if (!arst3)
  62                 q <= 0;
  63         else
  64                 q <= d;
  65 end
  66 endmodule
  67
  68 // SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of
  69 // simulation-implementation mismatches. The following testcases try to cover the
  70 // part that is defined and avoid the undefined cases.
  71
  72 module dffsr1(clk, arst, d, q);
  73 input clk, arst, d;
  74 output reg q;
  75 always @(posedge clk, posedge arst) begin
  76         if (arst)
  77                 q <= d^d; // constant expression -- but the frontend optimizer does not know that..
  78         else
  79                 q <= d;
  80 end
  81 endmodule
  82
  83 module dffsr2(clk, preset, clear, d, q);
  84 input clk, preset, clear, d;
  85 output q;
  86 (* gentb_clock *)
  87 wire clk, preset, clear, d;
  88 dffsr2_sub uut (clk, preset && !clear, !preset && clear, d, q);
  89 endmodule
  90
  91 (* gentb_skip *)
  92 module dffsr2_sub(clk, preset, clear, d, q);
  93 input clk, preset, clear, d;
  94 output reg q;
  95 always @(posedge clk, posedge preset, posedge clear) begin
  96         if (preset)
  97                 q <= 1;
  98         else if (clear)
  99                 q <= 0;
 100         else
 101                 q <= d;
 102 end
 103 endmodule
 104
 105