tests/simple/dff_init.v

   1 module dff0_test(n1, n1_inv, clk);
   2   input clk;
   3   output n1;
   4   reg n1 = 32'd0;
   5   output n1_inv;
   6   always @(posedge clk)
   7       n1 <= n1_inv;
   8   assign n1_inv = ~n1;
   9 endmodule
  10
  11 module dff1_test(n1, n1_inv, clk);
  12   input clk;
  13   (* init = 32'd1 *)
  14   output n1;
  15   reg n1 = 32'd1;
  16   output n1_inv;
  17   always @(posedge clk)
  18       n1 <= n1_inv;
  19   assign n1_inv = ~n1;
  20 endmodule
  21
  22 module dff0a_test(n1, n1_inv, clk);
  23   input clk;
  24   (* init = 32'd0 *) // Must be consistent with reg initialiser below
  25   output n1;
  26   reg n1 = 32'd0;
  27   output n1_inv;
  28   always @(posedge clk)
  29       n1 <= n1_inv;
  30   assign n1_inv = ~n1;
  31 endmodule
  32
  33 module dff1a_test(n1, n1_inv, clk);
  34   input clk;
  35   (* init = 32'd1 *) // Must be consistent with reg initialiser below
  36   output n1;
  37   reg n1 = 32'd1;
  38   output n1_inv;
  39   always @(posedge clk)
  40       n1 <= n1_inv;
  41   assign n1_inv = ~n1;
  42 endmodule
  43
  44 module dff_test_997 (y, clk, wire4);
  45 // https://github.com/YosysHQ/yosys/issues/997
  46    output wire [1:0] y;
  47    input             clk;
  48    input signed      wire4;
  49    reg [1:0]  reg10 = 0;
  50    always @(posedge clk) begin
  51       reg10 <= wire4;
  52    end
  53    assign y = reg10;
  54 endmodule