tests/simple/dynslice.v

   1 module dynslice (
   2     input clk ,
   3     input [9:0] ctrl ,
   4     input [15:0] din ,
   5     input [3:0] sel ,
   6     output reg [127:0] dout
   7 );
   8 always @(posedge clk)
   9 begin
  10     dout[ctrl*sel+:16] <= din ;
  11 end
  12 endmodule