1 // borrowed with some modifications from
2 // http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html
3 module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out);
8 output reg [8:0] count_out;
9 output reg carry_out, borrow_out, parity_out;
11 reg [9:0] cnt_up, cnt_dn;
14 always @(posedge clock)
16 cnt_dn = count_out - 3'b 101;
17 cnt_up = count_out + 2'b 11;
20 2'b 00 : count_nxt = data_in;
21 2'b 01 : count_nxt = cnt_dn;
22 2'b 10 : count_nxt = cnt_up;
23 2'b 11 : count_nxt = count_out;
24 default : count_nxt = 9'bX;
27 parity_out <= ^count_nxt;
28 carry_out <= up & cnt_up[9];
29 borrow_out <= down & cnt_dn[9];
30 count_out <= count_nxt;