fail svinterfaces testcases on yosys error exit
[yosys.git] / tests / simple / forgen01.v
1
2 // VERIFIC-SKIP
3
4 module uut_forgen01(a, y);
5
6 input [4:0] a;
7 output y;
8
9 integer i, j;
10 reg [31:0] lut;
11
12 initial begin
13 for (i = 0; i < 32; i = i+1) begin
14 lut[i] = i > 1;
15 for (j = 2; j*j <= i; j = j+1)
16 if (i % j == 0)
17 lut[i] = 0;
18 end
19 end
20
21 assign y = lut[a];
22
23 endmodule