tests/simple/fsm.v

   1
   2 // `define ASYNC_RESET
   3
   4 module fsm_test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
   5
   6 input clk, reset, button_a, button_b;
   7 output reg red_a, green_a, red_b, green_b;
   8
   9 (* gentb_constant = 0 *)
  10 wire reset;
  11
  12 integer state;
  13 reg [3:0] cnt;
  14
  15 `ifdef ASYNC_RESET
  16 always @(posedge clk, posedge reset)
  17 `else
  18 always @(posedge clk)
  19 `endif
  20 begin
  21         cnt <= 0;
  22         red_a <= 1;
  23         red_b <= 1;
  24         green_a <= 0;
  25         green_b <= 0;
  26
  27         if (reset)
  28                 state <= 100;
  29         else
  30                 case (state)
  31                         100: begin
  32                                 if (button_a && !button_b)
  33                                         state <= 200;
  34                                 if (!button_a && button_b)
  35                                         state <= 300;
  36                         end
  37                         200: begin
  38                                 red_a <= 0;
  39                                 green_a <= 1;
  40                                 cnt <= cnt + 1;
  41                                 if (cnt == 5)
  42                                         state <= 210;
  43                         end
  44                         210: begin
  45                                 red_a <= 0;
  46                                 green_a <= cnt[0];
  47                                 cnt <= cnt + 1;
  48                                 if (cnt == 10)
  49                                         state <= 100;
  50                         end
  51                         300: begin
  52                                 red_b <= 0;
  53                                 green_b <= 1;
  54                                 cnt <= cnt + 1;
  55                                 if (cnt == 5)
  56                                         state <= 310;
  57                         end
  58                         310: begin
  59                                 red_b <= 0;
  60                                 green_b <= cnt[0];
  61                                 cnt <= cnt + 1;
  62                                 if (cnt == 10)
  63                                         state <= 100;
  64                         end
  65                 endcase
  66 end
  67
  68 endmodule
  69