tests/simple/genblk_dive.v

   1 `default_nettype none
   2 module top(output wire x);
   3         generate
   4                 if (1) begin : Z
   5                         if (1) begin : A
   6                                 wire x;
   7                                 if (1) begin : B
   8                                         wire x;
   9                                         if (1) begin : C
  10                                                 wire x;
  11                                                 assign B.x = 0;
  12                                                 wire z = A.B.C.x;
  13                                         end
  14                                         assign A.x = A.B.C.x;
  15                                 end
  16                                 assign B.C.x = B.x;
  17                         end
  18                 end
  19         endgenerate
  20         assign x = Z.A.x;
  21 endmodule