1 module graphtest (A,B,X,Y,Z);
11 assign t[4] = 1'b0; // Constant connects to wire
12 assign t[2:0] = A[2:0] & { 2'b10, B[3]}; // Concatenation of intermediate wire
13 assign t[3] = A[2] ^ B[3]; // Bitwise-XOR
15 // assign Y[2:0] = 3'b111;
17 // assign Y[9:7] = t[0:2];
18 assign Y = {3'b111, A, t[2:0]}; // Direct assignment of concatenation
20 assign Z[0] = 1'b0; // Constant connects to PO
21 assign Z[1] = t[3]; // Intermediate sig connects to PO
22 assign Z[3:2] = A[2:1]; // PI connects to PO
23 assign Z[7:4] = {1'b0, B[2:0]}; // Concat of CV and PI connect to PO
26 if (A == 4'b1111) begin // All-Const at port (eq)
30 X = 4'b0000; // All-Const at port (mux)