tests/simple/hierarchy.v

   1
   2 (* top *)
   3 module top(a, b, y1, y2, y3, y4);
   4 input [3:0] a;
   5 input signed [3:0] b;
   6 output [7:0] y1, y2, y3, y4;
   7
   8 // this version triggers a bug in Icarus Verilog
   9 // submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
  10
  11 // this version is handled correctly by Icarus Verilog
  12 submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
  13
  14 endmodule
  15
  16 (* gentb_skip *)
  17 module submod(a, b, y1, y2, y3, y4);
  18 parameter c = 0;
  19 parameter [7:0] d = 0;
  20 input [3:0] a, b;
  21 output [7:0] y1, y2, y3, y4;
  22 assign y1 = a;
  23 assign y2 = b;
  24 assign y3 = c;
  25 assign y4 = d;
  26 endmodule
  27