Merge pull request #1814 from YosysHQ/mmicko/pyosys_makefile
[yosys.git] / tests / simple / hierdefparam.v
1 `default_nettype none
2
3 module hierdefparam_top(input [7:0] A, output [7:0] Y);
4 generate begin:foo
5 hierdefparam_a mod_a(.A(A), .Y(Y));
6 end endgenerate
7 defparam foo.mod_a.bar[0].mod_b.addvalue = 42;
8 defparam foo.mod_a.bar[1].mod_b.addvalue = 43;
9 endmodule
10
11 module hierdefparam_a(input [7:0] A, output [7:0] Y);
12 genvar i;
13 generate
14 for (i = 0; i < 2; i=i+1) begin:bar
15 wire [7:0] a, y;
16 hierdefparam_b mod_b(.A(a), .Y(y));
17 end
18 endgenerate
19 assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y;
20 endmodule
21
22 module hierdefparam_b(input [7:0] A, output [7:0] Y);
23 parameter [7:0] addvalue = 44;
24 assign Y = A + addvalue;
25 endmodule