1 // one of my early test cases was the OpenCores I2C master
2 // This is a collection of stripped down code snippets from
3 // this core that triggered bugs in early versions of yosys.
5 // from i2c_master_bit_ctrl
6 module i2c_test01(clk, rst, nReset, al);
8 input clk, rst, nReset;
12 always @(posedge clk or negedge nReset)
18 always @(posedge clk or negedge nReset)
28 // from i2c_master_bit_ctrl
29 module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
31 input clk, slave_wait, clk_cnt;
37 output reg [15:0] cnt;
53 cnt <= #1 cnt - 16'h1;