tests/simple/i2c_master_tests.v

   1 // one of my early test cases was the OpenCores I2C master
   2 // This is a collection of stripped down code snippets from
   3 // this core that triggered bugs in early versions of yosys.
   4
   5 // from i2c_master_bit_ctrl
   6 module i2c_test01(clk, rst, nReset, al);
   7
   8         input clk, rst, nReset;
   9         output reg al;
  10
  11         reg cmd_stop;
  12         always @(posedge clk or negedge nReset)
  13           if (~nReset)
  14             cmd_stop <= #1 1'b0;
  15           else if (rst)
  16             cmd_stop <= #1 1'b0;
  17
  18         always @(posedge clk or negedge nReset)
  19           if (~nReset)
  20             al <= #1 1'b0;
  21           else if (rst)
  22             al <= #1 1'b0;
  23           else
  24             al <= #1 ~cmd_stop;
  25
  26 endmodule
  27
  28 // from i2c_master_bit_ctrl
  29 module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
  30
  31         input clk, slave_wait, clk_cnt;
  32         input cmd;
  33
  34         output reg cmd_stop;
  35
  36         reg clk_en;
  37         output reg [15:0] cnt;
  38
  39         always @(posedge clk)
  40           if (~|cnt)
  41             if (~slave_wait)
  42               begin
  43                   cnt    <= #1 clk_cnt;
  44                   clk_en <= #1 1'b1;
  45               end
  46             else
  47               begin
  48                   cnt    <= #1 cnt;
  49                   clk_en <= #1 1'b0;
  50               end
  51           else
  52             begin
  53                 cnt    <= #1 cnt - 16'h1;
  54                 clk_en <= #1 1'b0;
  55             end
  56
  57         always @(posedge clk)
  58           if (clk_en)
  59             cmd_stop <= #1 cmd;
  60
  61 endmodule
  62