Merge pull request #1814 from YosysHQ/mmicko/pyosys_makefile
[yosys.git] / tests / simple / implicit_ports.v
1 // Test implicit port connections
2 module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
3 assign cout = cin;
4 assign result = a + b;
5 endmodule
6
7 module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
8 wire cin = 1;
9 alu alu (
10 .a(a),
11 .b, // Implicit connection is equivalent to .b(b)
12 .cin(), // Explicitely unconnected
13 .cout(cout),
14 .result(alu_result)
15 );
16 endmodule