tests/simple/loops.v

   1
   2 // a simple test case extracted from systemcaes (as included in iwls2005)
   3 // this design has latches (or logic loops) for the two temp variables.
   4 // this latches (or logic loops) must be removed in the final synthesis results
   5
   6 module aes(
   7         // inputs
   8         input [3:0] addroundkey_data_i,
   9         input [3:0] addroundkey_data_reg,
  10         input [3:0] addroundkey_round,
  11         input [3:0] key_i,
  12         input [3:0] keysched_new_key_o,
  13         input [3:0] round,
  14         input addroundkey_start_i,
  15         input keysched_ready_o,
  16
  17         // outputs
  18         output reg [3:0] keysched_last_key_i,
  19         output reg [3:0] keysched_round_i,
  20         output reg [3:0] next_addroundkey_data_reg,
  21         output reg [3:0] next_addroundkey_round,
  22         output reg [3:0] round_data_var,
  23         output reg keysched_start_i,
  24         output reg next_addroundkey_ready_o
  25 );
  26
  27 // temp variables
  28 reg [3:0] data_var;
  29 reg [3:0] round_key_var;
  30
  31 always @*
  32 begin
  33         keysched_start_i = 0;
  34         keysched_round_i = addroundkey_round;
  35         round_data_var = addroundkey_data_reg;
  36         next_addroundkey_data_reg = addroundkey_data_reg;
  37         next_addroundkey_ready_o = 0;
  38         next_addroundkey_round = addroundkey_round;
  39
  40         if (addroundkey_round == 1 || addroundkey_round == 0)
  41                 keysched_last_key_i = key_i;
  42         else
  43                 keysched_last_key_i = keysched_new_key_o;
  44
  45         if (round == 0 && addroundkey_start_i)
  46         begin
  47                 data_var = addroundkey_data_i;
  48                 round_key_var = key_i;
  49                 round_data_var = round_key_var ^ data_var;
  50                 next_addroundkey_data_reg = round_data_var;
  51                 next_addroundkey_ready_o = 1;
  52         end
  53         else if (addroundkey_start_i && round != 0)
  54         begin
  55                 keysched_last_key_i = key_i;
  56                 keysched_start_i = 1;
  57                 keysched_round_i = 1;
  58                 next_addroundkey_round = 1;
  59         end
  60         else if (addroundkey_round != round && keysched_ready_o)
  61         begin
  62                 next_addroundkey_round = addroundkey_round + 1;
  63                 keysched_last_key_i = keysched_new_key_o;
  64                 keysched_start_i = 1;
  65                 keysched_round_i = addroundkey_round + 1;
  66         end
  67         else if (addroundkey_round == round && keysched_ready_o)
  68         begin
  69                 data_var = addroundkey_data_i;
  70                 round_key_var = keysched_new_key_o;
  71                 round_data_var = round_key_var ^ data_var;
  72                 next_addroundkey_data_reg = round_data_var;
  73                 next_addroundkey_ready_o = 1;
  74                 next_addroundkey_round = 0;
  75         end
  76 end
  77
  78 endmodule
  79