tests/simple/mem2reg.v

   1
   2 module mem2reg_test1(in_addr, in_data, out_addr, out_data);
   3
   4 input [1:0] in_addr, out_addr;
   5 input [3:0] in_data;
   6 output reg [3:0] out_data;
   7
   8 reg [3:0] array [2:0];
   9
  10 always @* begin
  11         array[0] = 0;
  12         array[1] = 23;
  13         array[2] = 42;
  14         array[in_addr] = in_data;
  15         out_data = array[out_addr];
  16 end
  17
  18 endmodule
  19
  20 // ------------------------------------------------------
  21
  22 module mem2reg_test2(clk, reset, mode, addr, data);
  23
  24 input clk, reset, mode;
  25 input [2:0] addr;
  26 output [3:0] data;
  27
  28 (* mem2reg *)
  29 reg [3:0] mem [0:7];
  30
  31 assign data = mem[addr];
  32
  33 integer i;
  34
  35 always @(posedge clk) begin
  36         if (reset) begin
  37                 for (i=0; i<8; i=i+1)
  38                         mem[i] <= i;
  39         end else
  40         if (mode) begin
  41                 for (i=0; i<8; i=i+1)
  42                         mem[i] <= mem[i]+1;
  43         end else begin
  44                 mem[addr] <= 0;
  45         end
  46 end
  47
  48 endmodule
  49
  50 // ------------------------------------------------------
  51
  52 // http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
  53 module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
  54 reg [7:0] dint_c [0:7];
  55 always @(posedge clk)
  56   begin
  57       {dout_a[0], dint_c[3]} <= din_a;
  58   end
  59 assign dout_b = dint_c[3];
  60 endmodule
  61
  62 // ------------------------------------------------------
  63
  64 module mem2reg_test4(result1, result2, result3);
  65         output signed [9:0] result1;
  66         output signed [9:0] result2;
  67         output signed [9:0] result3;
  68
  69         wire signed [9:0] intermediate [0:3];
  70
  71         function integer depth2Index;
  72                 input integer depth;
  73                 depth2Index = depth;
  74         endfunction
  75
  76         assign intermediate[depth2Index(1)] = 1;
  77         assign intermediate[depth2Index(2)] = 2;
  78         assign intermediate[3] = 3;
  79         assign result1 = intermediate[1];
  80         assign result2 = intermediate[depth2Index(2)];
  81         assign result3 = intermediate[depth2Index(3)];
  82 endmodule
  83
  84 // ------------------------------------------------------
  85
  86 module mem2reg_test5(input ctrl, output out);
  87         wire [0:0] foo[0:0];
  88         wire [0:0] bar[0:1];
  89
  90         assign foo[0] = ctrl;
  91         assign bar[0] = 0, bar[1] = 1;
  92         assign out = bar[foo[0]];
  93 endmodule
  94
  95 // ------------------------------------------------------
  96
  97 module mem2reg_test6 (din, dout);
  98         input   wire    [3:0] din;
  99         output  reg     [3:0] dout;
 100
 101         reg [1:0] din_array  [1:0];
 102         reg [1:0] dout_array [1:0];
 103
 104         always @* begin
 105                 din_array[0] = din[0 +: 2];
 106                 din_array[1] = din[2 +: 2];
 107
 108                 dout_array[0] = din_array[0];
 109                 dout_array[1] = din_array[1];
 110
 111                 {dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
 112
 113                 dout[0 +: 2] = dout_array[0];
 114                 dout[2 +: 2] = dout_array[1];
 115         end
 116 endmodule