tests/simple/mem_arst.v

   1
   2 module MyMem #(
   3   parameter AddrWidth = 4,
   4   parameter DataWidth = 4) (
   5   (* gentb_constant = 1 *)
   6   input                  Reset_n_i,
   7   input                  Clk_i,
   8   input  [AddrWidth-1:0] Addr_i,
   9   input  [DataWidth-1:0] Data_i,
  10   output [DataWidth-1:0] Data_o,
  11   input                  WR_i);
  12
  13   reg [DataWidth-1:0] Data_o;
  14
  15   localparam Size = 2**AddrWidth;
  16
  17   (* mem2reg *)
  18   reg [DataWidth-1:0] Mem[Size-1:0];
  19
  20   integer i;
  21
  22   always @(negedge Reset_n_i or posedge Clk_i)
  23   begin
  24     if (!Reset_n_i)
  25     begin
  26       Data_o <= 'bx;
  27       for (i=0; i<Size; i=i+1)
  28       begin
  29         Mem[i] <= 0;
  30       end
  31     end
  32     else
  33     begin
  34       Data_o <= Mem[Addr_i];
  35       if (WR_i)
  36       begin
  37         Mem[Addr_i] <= Data_i;
  38       end
  39     end
  40   end
  41
  42 endmodule
  43