tests/simple/memory.v

   1
   2 module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
   3
   4 input clk, wr_en;
   5 input [3:0] wr_addr, rd_addr;
   6 input [7:0] wr_value;
   7 output reg [7:0] rd_value;
   8
   9 reg [7:0] data [15:0];
  10
  11 always @(posedge clk)
  12         if (wr_en)
  13                 data[wr_addr] <= wr_value;
  14
  15 always @(posedge clk)
  16         rd_value <= data[rd_addr];
  17
  18 endmodule
  19