tests/simple/memory.v

   1
   2 module memtest00(clk, setA, setB, y);
   3
   4 input clk, setA, setB;
   5 output y;
   6 reg mem [1:0];
   7
   8 always @(posedge clk) begin
   9         if (setA) mem[0] <= 0;  // this is line 9
  10         if (setB) mem[0] <= 1;  // this is line 10
  11 end
  12
  13 assign y = mem[0];
  14
  15 endmodule
  16
  17 // ----------------------------------------------------------
  18
  19 module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
  20
  21 input clk, wr_en;
  22 input [3:0] wr_addr, rd_addr;
  23 input [7:0] wr_value;
  24 output reg [7:0] rd_value;
  25
  26 reg [7:0] data [15:0];
  27
  28 always @(posedge clk)
  29         if (wr_en)
  30                 data[wr_addr] <= wr_value;
  31
  32 always @(posedge clk)
  33         rd_value <= data[rd_addr];
  34
  35 endmodule
  36
  37 // ----------------------------------------------------------
  38
  39 module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
  40
  41 input clk, setA, setB;
  42 input [1:0] addr;
  43 input [2:0] bit;
  44 output reg y1, y2;
  45 output y3, y4;
  46
  47 reg [7:0] mem1 [3:0];
  48
  49 (* mem2reg *)
  50 reg [7:0] mem2 [3:0];
  51
  52 always @(posedge clk) begin
  53         if (setA) begin
  54                 mem1[0] <= 10;
  55                 mem1[1] <= 20;
  56                 mem1[2] <= 30;
  57                 mem2[0] <= 17;
  58                 mem2[1] <= 27;
  59                 mem2[2] <= 37;
  60         end
  61         if (setB) begin
  62                 mem1[0] <=  1;
  63                 mem1[1] <=  2;
  64                 mem1[2] <=  3;
  65                 mem2[0] <= 71;
  66                 mem2[1] <= 72;
  67                 mem2[2] <= 73;
  68         end
  69         y1 <= mem1[addr][bit];
  70         y2 <= mem2[addr][bit];
  71 end
  72
  73 assign y3 = mem1[addr][bit];
  74 assign y4 = mem2[addr][bit];
  75
  76 endmodule
  77
  78 // ----------------------------------------------------------
  79
  80 module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
  81
  82 input clk, wr_enable;
  83 input [3:0] wr_addr, wr_data, rd_addr;
  84 output reg [3:0] rd_data;
  85
  86 reg [3:0] memory [0:15];
  87
  88 always @(posedge clk) begin
  89         if (wr_enable)
  90                 memory[wr_addr] <= wr_data;
  91         rd_data <= memory[rd_addr];
  92 end
  93
  94 endmodule
  95
  96 // ----------------------------------------------------------
  97
  98 module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
  99
 100 input clk, wr_enable;
 101 input [3:0] wr_addr, wr_data, rd_addr;
 102 output [3:0] rd_data;
 103
 104 reg rd_addr_buf;
 105 reg [3:0] memory [0:15];
 106
 107 always @(posedge clk) begin
 108         if (wr_enable)
 109                 memory[wr_addr] <= wr_data;
 110         rd_addr_buf <= rd_addr;
 111 end
 112
 113 assign rd_data = memory[rd_addr_buf];
 114
 115 endmodule
 116
 117 // ----------------------------------------------------------
 118
 119 module memtest05(clk, addr, wdata, rdata, wen);
 120
 121 input clk;
 122 input [1:0] addr;
 123 input [7:0] wdata;
 124 output reg [7:0] rdata;
 125 input [3:0] wen;
 126
 127 reg [7:0] mem [0:3];
 128
 129 integer i;
 130 always @(posedge clk) begin
 131         for (i = 0; i < 4; i = i+1)
 132                 if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
 133         rdata <= mem[addr];
 134 end
 135
 136 endmodule
 137
 138 // ----------------------------------------------------------
 139
 140 module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
 141     (* gentb_constant=0 *) wire rst;
 142     reg [7:0] test [0:7];
 143     integer i;
 144     always @(posedge clk) begin
 145         if (rst) begin
 146             for (i=0; i<8; i=i+1)
 147                 test[i] <= 0;
 148         end else begin
 149             test[0][2] <= din[1];
 150             test[0][5] <= test[0][2];
 151             test[idx][3] <= din[idx];
 152             test[idx][6] <= test[idx][2];
 153             test[idx][idx] <= !test[idx][idx];
 154         end
 155     end
 156     assign dout = test[idx];
 157 endmodule
 158
 159 module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
 160     (* gentb_constant=0 *) wire rst;
 161     reg [7:0] test [0:7];
 162     integer i;
 163     always @(posedge clk or posedge rst) begin
 164         if (rst) begin
 165             for (i=0; i<8; i=i+1)
 166                 test[i] <= 0;
 167         end else begin
 168             test[0][2] <= din[1];
 169             test[0][5] <= test[0][2];
 170             test[idx][3] <= din[idx];
 171             test[idx][6] <= test[idx][2];
 172             test[idx][idx] <= !test[idx][idx];
 173         end
 174     end
 175     assign dout = test[idx];
 176 endmodule
 177
 178 // ----------------------------------------------------------
 179
 180 module memtest07(clk, addr, woffset, wdata, rdata);
 181
 182 input clk;
 183 input [1:0] addr;
 184 input [3:0] wdata;
 185 input [1:0] woffset;
 186 output reg [7:0] rdata;
 187
 188 reg [7:0] mem [0:3];
 189
 190 integer i;
 191 always @(posedge clk) begin
 192         mem[addr][woffset +: 4] <= wdata;
 193         rdata <= mem[addr];
 194 end
 195
 196 endmodule
 197
 198 // ----------------------------------------------------------
 199
 200 module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y);
 201         reg [3:0] mem [0:15] [0:15];
 202         always @(posedge clk) begin
 203                 y <= mem[a][b];
 204                 mem[a][b] <= c;
 205         end
 206 endmodule
 207
 208 // ----------------------------------------------------------
 209
 210 module memtest09 (
 211     input clk,
 212     input [3:0] a_addr, a_din, b_addr, b_din,
 213     input a_wen, b_wen,
 214     output reg [3:0] a_dout, b_dout
 215 );
 216     reg [3:0] memory [10:35];
 217
 218     always @(posedge clk) begin
 219         if (a_wen)
 220             memory[10 + a_addr] <= a_din;
 221         a_dout <= memory[10 + a_addr];
 222     end
 223
 224     always @(posedge clk) begin
 225         if (b_wen && (10 + a_addr != 20 + b_addr || !a_wen))
 226             memory[20 + b_addr] <= b_din;
 227         b_dout <= memory[20 + b_addr];
 228     end
 229 endmodule
 230
 231 // ----------------------------------------------------------
 232
 233 module memtest10(input clk, input [5:0] din, output [5:0] dout);
 234         reg [5:0] queue [0:3];
 235         integer i;
 236
 237         always @(posedge clk) begin
 238                 queue[0] <= din;
 239                 for (i = 1; i < 4; i=i+1) begin
 240                         queue[i] <= queue[i-1];
 241                 end
 242         end
 243
 244         assign dout = queue[3];
 245 endmodule
 246
 247 // ----------------------------------------------------------
 248
 249 module memtest11(clk, wen, waddr, raddr, wdata, rdata);
 250         input clk, wen;
 251         input [1:0] waddr, raddr;
 252         input [7:0] wdata;
 253         output [7:0] rdata;
 254
 255         reg [7:0] mem [3:0];
 256
 257         assign rdata = mem[raddr];
 258
 259         always @(posedge clk) begin
 260                 if (wen)
 261                         mem[waddr] <= wdata;
 262                 else
 263                         mem[waddr] <= mem[waddr];
 264         end
 265 endmodule
 266
 267 // ----------------------------------------------------------
 268
 269 module memtest12 (
 270    input clk,
 271    input [1:0] adr,
 272    input [1:0] din,
 273    output reg [1:0] q
 274 );
 275    reg [1:0] ram [3:0];
 276    always@(posedge clk)
 277      {ram[adr], q} <= {din, ram[adr]};
 278 endmodule
 279
 280 // ----------------------------------------------------------
 281
 282 module memtest13 (
 283         input clk, rst,
 284         input [1:0] a1, a2, a3, a4, a5, a6,
 285         input [3:0] off1, off2,
 286         input [31:5] din1,
 287         input [3:0] din2, din3,
 288         output reg [3:0] dout1, dout2,
 289         output reg [31:5] dout3
 290 );
 291         reg [31:5] mem [0:3];
 292
 293         always @(posedge clk) begin
 294                 if (rst) begin
 295                         mem[0] <= 0;
 296                         mem[1] <= 0;
 297                         mem[2] <= 0;
 298                         mem[3] <= 0;
 299                 end else begin
 300                         mem[a1] <= din1;
 301                         mem[a2][14:11] <= din2;
 302                         mem[a3][5 + off1 +: 4] <= din3;
 303                         dout1 <= mem[a4][12:9];
 304                         dout2 <= mem[a5][5 + off2 +: 4];
 305                         dout3 <= mem[a6];
 306                 end
 307         end
 308 endmodule
 309