tests/simple/muxtree.v

   1
   2 // test case generated from IWLS 2005 usb_phy core
   3 // (triggered a bug in opt_muxtree pass)
   4
   5 module usb_tx_phy(clk, rst, DataOut_i, TxValid_i, hold_reg);
   6
   7 input           clk;
   8 input           rst;
   9 input           DataOut_i;
  10 input           TxValid_i;
  11 output reg      hold_reg;
  12
  13 reg             state, next_state;
  14 reg             ld_sop_d;
  15 reg             ld_data_d;
  16
  17 always @(posedge clk)
  18         if(ld_sop_d)
  19                 hold_reg <= 0;
  20         else
  21                 hold_reg <= DataOut_i;
  22
  23 always @(posedge clk)
  24         if(!rst)        state <= 0;
  25         else            state <= next_state;
  26
  27 always @(state or TxValid_i)
  28    begin
  29         next_state = state;
  30
  31         ld_sop_d = 1'b0;
  32         ld_data_d = 1'b0;
  33
  34         case(state)     // synopsys full_case parallel_case
  35            0:
  36                         if(TxValid_i)
  37                            begin
  38                                 ld_sop_d = 1'b1;
  39                                 next_state = 1;
  40                            end
  41            1:
  42                         if(TxValid_i)
  43                            begin
  44                                 ld_data_d = 1'b1;
  45                                 next_state = 0;
  46                            end
  47         endcase
  48    end
  49
  50 endmodule
  51
  52
  53 // test case inspired by softusb_navre code:
  54 // default not as last case
  55
  56 module default_cases(a, y);
  57
  58 input [2:0] a;
  59 output reg [3:0] y;
  60
  61 always @* begin
  62         case (a)
  63                 3'b000, 3'b111: y <= 0;
  64                 default: y <= 4;
  65                 3'b001: y <= 1;
  66                 3'b010: y <= 2;
  67                 3'b100: y <= 3;
  68         endcase
  69 end
  70
  71 endmodule
  72
  73
  74 // test case for muxtree with select on leaves
  75
  76 module select_leaves(input R, C, D, output reg Q);
  77         always @(posedge C)
  78                 if (!R)
  79                         Q <= R;
  80                 else
  81                         Q <= Q ? Q : D ? D : Q;
  82 endmodule
  83