tests/simple/partsel.v

   1 module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
   2 wire [5:0] offset = idx << 2;
   3 assign slice_up = data[offset +: 4];
   4 assign slice_down = data[offset + 3 -: 4];
   5 endmodule
   6
   7 module partsel_test002 (
   8         input clk, rst,
   9         input [7:0] a,
  10         input [0:7] b,
  11         input [1:0] s,
  12         output [7:0] x1, x2, x3,
  13         output [0:7] x4, x5, x6,
  14         output [7:0] y1, y2, y3,
  15         output [0:7] y4, y5, y6,
  16         output [7:0] z1, z2, z3,
  17         output [0:7] z4, z5, z6,
  18         output [7:0] w1, w2, w3,
  19         output [0:7] w4, w5, w6,
  20         output [7:0] p1, p2, p3, p4, p5, p6,
  21         output [0:7] q1, q2, q3, q4, q5, q6,
  22         output reg [7:0] r1,
  23         output reg [0:7] r2
  24 );
  25
  26 assign x1 = a, x2 = a + b, x3 = b;
  27 assign x4 = a, x5 = a + b, x6 = b;
  28 assign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3];
  29 assign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3];
  30 assign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3];
  31 assign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3];
  32 assign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6];
  33 assign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6];
  34 assign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];
  35 assign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];
  36
  37 always @(posedge clk) begin
  38         if (rst) begin
  39                 { r1, r2 } = 16'h1337 ^ {a, b};
  40         end else begin
  41                 case (s)
  42                         0: begin
  43                                 r1[3:0] <= r2[0:3] ^ x1;
  44                                 r2[4:7] <= r1[7:4] ^ x4;
  45                         end
  46                         1: begin
  47                                 r1[2 +: 3] <= r2[5 -: 3] + x1;
  48                                 r2[3 +: 3] <= r1[6 -: 3] + x4;
  49                         end
  50                         2: begin
  51                                 r1[6 -: 3] <= r2[3 +: 3] - x1;
  52                                 r2[7 -: 3] <= r1[4 +: 3] - x4;
  53                         end
  54                         3: begin
  55                                 r1 <= r2;
  56                                 r2 <= r1;
  57                         end
  58                 endcase
  59         end
  60 end
  61
  62 endmodule
  63
  64 module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
  65 assign dout = din[a*b +: 2];
  66 endmodule
  67
  68 module partsel_test004 (
  69         input [31:0] din,
  70         input signed [4:0] n,
  71         output reg [31:0] dout
  72 );
  73         always @(*) begin
  74                 dout = 0;
  75                 dout[n+1 +: 2] = din[n +: 2];
  76         end
  77 endmodule
  78
  79
  80 module partsel_test005 (
  81         input [31:0] din,
  82         input signed [4:0] n,
  83         output reg [31:0] dout
  84 );
  85         always @(*) begin
  86                 dout = 0;
  87                 dout[n+1] = din[n];
  88         end
  89 endmodule
  90
  91 module partsel_test006 (
  92         input [31:0] din,
  93         input signed [4:0] n,
  94         output reg [31:-32] dout
  95 );
  96         always @(*) begin
  97                 dout = 0;
  98                 dout[n+1 +: 2] = din[n +: 2];
  99         end
 100 endmodule
 101
 102
 103 module partsel_test007 (
 104         input [31:0] din,
 105         input signed [4:0] n,
 106         output reg [31:-32] dout
 107 );
 108         always @(*) begin
 109                 dout = 0;
 110                 dout[n+1] = din[n];
 111         end
 112 endmodule