2 module blocking_cond (in, out);
19 // -------------------------------------------------------------
21 module uut(clk, arst, a, b, c, d, e, f, out1);
23 input clk, arst, a, b, c, d, e, f;
24 output reg [3:0] out1;
26 always @(posedge clk, posedge arst) begin
57 // -------------------------------------------------------------
59 // extracted from ../asicworld/code_hdl_models_uart.v
60 // (triggered a bug in the proc_mux pass)
61 module uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt);
68 output reg [3:0] tx_cnt;
70 always @ (posedge txclk)