tests/simple/process.v

   1
   2 module blocking_cond (in, out);
   3
   4 input in;
   5 output reg out;
   6 reg tmp;
   7
   8 always @* begin
   9         tmp = 1;
  10         out = 1'b0;
  11         case (1'b1)
  12                 tmp: out = in;
  13         endcase
  14         tmp = 0;
  15 end
  16
  17 endmodule
  18
  19 // -------------------------------------------------------------
  20
  21 module uut(clk, arst, a, b, c, d, e, f,  out1);
  22
  23 input clk, arst, a, b, c, d, e, f;
  24 output reg [3:0] out1;
  25
  26 always @(posedge clk, posedge arst) begin
  27         if (arst)
  28                 out1 = 0;
  29         else begin
  30                 if (a) begin
  31                         case ({b, c})
  32                                 2'b00:
  33                                         out1 = out1 + 9;
  34                                 2'b01, 2'b10:
  35                                         out1 = out1 + 13;
  36                         endcase
  37                         if (d) begin
  38                                 out1 = out1 + 2;
  39                                 out1 = out1 + 1;
  40                         end
  41                         case ({e, f})
  42                                 2'b11:
  43                                         out1 = out1 + 8;
  44                                 2'b00:
  45                                         ;
  46                                 default:
  47                                         out1 = out1 + 10;
  48                         endcase
  49                         out1 = out1 ^ 7;
  50                 end
  51                 out1 = out1 + 14;
  52         end
  53 end
  54
  55 endmodule
  56
  57 // -------------------------------------------------------------
  58
  59 // extracted from ../asicworld/code_hdl_models_uart.v
  60 // (triggered a bug in the proc_mux pass)
  61 module uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt);
  62
  63 input reset;
  64 input txclk;
  65 input ld_tx_data;
  66
  67 output reg tx_empty;
  68 output reg [3:0] tx_cnt;
  69
  70 always @ (posedge txclk)
  71 if (reset) begin
  72   tx_empty      <= 1;
  73   tx_cnt        <= 0;
  74 end else begin
  75    if (ld_tx_data) begin
  76      tx_empty <= 0;
  77    end
  78    if (!tx_empty) begin
  79      tx_cnt <= tx_cnt + 1;
  80    end
  81 end
  82
  83 endmodule
  84