Add opt_rmdff tests
[yosys.git] / tests / simple / repwhile.v
1 module repwhile_test001(input [5:0] a, output [7:0] y, output [31:0] x);
2
3 function [7:0] mylog2;
4 input [31:0] value;
5 begin
6 mylog2 = 0;
7 while (value > 0) begin
8 value = value >> 1;
9 mylog2 = mylog2 + 1;
10 end
11 end
12 endfunction
13
14 function [31:0] myexp2;
15 input [7:0] value;
16 begin
17 myexp2 = 1;
18 repeat (value)
19 myexp2 = myexp2 << 1;
20 end
21 endfunction
22
23 reg [7:0] y_table [63:0];
24 reg [31:0] x_table [63:0];
25
26 integer i;
27 initial begin
28 for (i = 0; i < 64; i = i+1) begin
29 y_table[i] <= mylog2(i);
30 x_table[i] <= myexp2(i);
31 end
32 end
33
34 assign y = y_table[a];
35 assign x = x_table[a];
36 endmodule