tests/simple/retime.v

   1 module retime_test(input clk, input [7:0] a, output z);
   2     reg [7:0] ff = 8'hF5;
   3     always @(posedge clk)
   4         ff <= {ff[6:0], ^a};
   5     assign z = ff[7];
   6 endmodule