tests/simple/rotate.v

   1
   2 // test case taken from amber23 Verilog code
   3 module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod);
   4
   5 input  [31:0] i_in;
   6 input         direction;
   7 input  [4:0]  shift_amount;
   8 output [31:0] rot_prod;
   9
  10 // Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
  11 // Practically a bit higher due to high fanout of "direction".
  12 generate
  13 genvar i, j;
  14         for (i = 0; i < 5; i = i + 1)
  15         begin : netgen
  16                 wire [31:0] in;
  17                 reg [31:0] out;
  18                 for (j = 0; j < 32; j = j + 1)
  19                 begin : net
  20                         always @*
  21                                 out[j] = in[j] & (~shift_amount[i] ^ direction) |
  22                                          in[wrap(j, i)] & (shift_amount[i] ^ direction);
  23                 end
  24         end
  25
  26         // Order is reverted with respect to volatile shift_amount[0]
  27         assign netgen[4].in = i_in;
  28         for (i = 1; i < 5; i = i + 1)
  29         begin : router
  30                 assign netgen[i-1].in = netgen[i].out;
  31         end
  32 endgenerate
  33
  34 // Aliasing
  35 assign rot_prod = netgen[0].out;
  36
  37 function [4:0] wrap;
  38 input integer pos;
  39 input integer level;
  40 integer out;
  41 begin
  42         out = pos - (1 << level);
  43         wrap = out[4:0];
  44 end
  45 endfunction
  46
  47 endmodule
  48