3 module usb_phy_test01(clk, rst, rx_en, fs_ce);
8 reg [1:0] dpll_next_state;
12 dpll_state <= rst ? 0 : dpll_next_state;
19 if(rx_en) dpll_next_state = 2'h0;
20 else dpll_next_state = 2'h1;
23 if(rx_en) dpll_next_state = 2'h3;
24 else dpll_next_state = 2'h2;
27 if(rx_en) dpll_next_state = 2'h0;
28 else dpll_next_state = 2'h3;
30 if(rx_en) dpll_next_state = 2'h0;
31 else dpll_next_state = 2'h0;