tests/simple/usb_phy_tests.v

   1
   2 // from usb_rx_phy
   3 module usb_phy_test01(clk, rst, rx_en, fs_ce);
   4
   5 input           clk, rst;
   6 input           rx_en;
   7 output reg      fs_ce;
   8 reg     [1:0]   dpll_next_state;
   9 reg     [1:0]   dpll_state;
  10
  11 always @(posedge clk)
  12         dpll_state <= rst ? 0 : dpll_next_state;
  13
  14 always @*
  15    begin
  16         fs_ce = 1'b0;
  17         case(dpll_state)
  18            2'h0:
  19                 if(rx_en)       dpll_next_state = 2'h0;
  20                 else            dpll_next_state = 2'h1;
  21            2'h1:begin
  22                 fs_ce = 1'b1;
  23                 if(rx_en)       dpll_next_state = 2'h3;
  24                 else            dpll_next_state = 2'h2;
  25                 end
  26            2'h2:
  27                 if(rx_en)       dpll_next_state = 2'h0;
  28                 else            dpll_next_state = 2'h3;
  29            2'h3:
  30                 if(rx_en)       dpll_next_state = 2'h0;
  31                 else            dpll_next_state = 2'h0;
  32         endcase
  33    end
  34
  35 endmodule
  36