tests/simple/xfirrtl

   1 # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
   2 arraycells.v    inst id[0] of
   3 defvalue.sv     Initial value not supported
   4 dff_different_styles.v
   5 dff_init.v      Initial value not supported
   6 generate.v      combinational loop
   7 hierdefparam.v  inst id[0] of
   8 i2c_master_tests.v   $adff
   9 implicit_ports.v     not fully initialized
  10 macros.v        drops modules
  11 mem2reg.v       drops modules
  12 mem_arst.v      $adff
  13 memory.v        $adff
  14 multiplier.v    inst id[0] of
  15 muxtree.v       drops modules
  16 omsp_dbg_uart.v $adff
  17 partsel.v       drops modules
  18 process.v       drops modules
  19 realexpr.v      drops modules
  20 retime.v        Initial value (11110101) for (retime_test.ff) not supported
  21 scopes.v        original verilog issues ( -x where x isn't declared signed)
  22 sincos.v        $adff
  23 specify.v       no code (empty module generates error
  24 subbytes.v      $adff
  25 task_func.v     drops modules
  26 values.v        combinational loop
  27 wandwor.v       Invalid connect to an expression that is not a reference or a WritePort.
  28 vloghammer.v    combinational loop
  29 wreduce.v       original verilog issues ( -x where x isn't declared signed)