tests/simple_abc9/abc9.v

   1 module abc9_test001(input a, output o);
   2 assign o = a;
   3 endmodule
   4
   5 module abc9_test002(input [1:0] a, output o);
   6 assign o = a[1];
   7 endmodule
   8
   9 module abc9_test003(input [1:0] a, output [1:0] o);
  10 assign o = a;
  11 endmodule
  12
  13 module abc9_test004(input [1:0] a, output o);
  14 assign o = ^a;
  15 endmodule
  16
  17 module abc9_test005(input [1:0] a, output o, output p);
  18 assign o = ^a;
  19 assign p = ~o;
  20 endmodule
  21
  22 module abc9_test006(input [1:0] a, output [2:0] o);
  23 assign o[0] = ^a;
  24 assign o[1] = ~o[0];
  25 assign o[2] = o[1];
  26 endmodule
  27
  28 module abc9_test007(input a, output o);
  29 wire b, c;
  30 assign c = ~a;
  31 assign b = c;
  32 abc9_test007_sub s(b, o);
  33 endmodule
  34
  35 module abc9_test007_sub(input a, output b);
  36 assign b = a;
  37 endmodule
  38
  39 module abc9_test008(input a, output o);
  40 wire b, c;
  41 assign b = ~a;
  42 assign c = b;
  43 abc9_test008_sub s(b, o);
  44 endmodule
  45
  46 module abc9_test008_sub(input a, output b);
  47 assign b = ~a;
  48 endmodule
  49
  50 module abc9_test009(inout io, input oe);
  51 reg latch;
  52 always @(io or oe)
  53     if (!oe)
  54         latch <= io;
  55 assign io = oe ? ~latch : 1'bz;
  56 endmodule
  57
  58 module abc9_test010(inout [7:0] io, input oe);
  59 reg [7:0] latch;
  60 always @(io or oe)
  61     if (!oe)
  62         latch <= io;
  63 assign io = oe ? ~latch : 8'bz;
  64 endmodule
  65
  66 module abc9_test011(inout io, input oe);
  67 reg latch;
  68 always @(io or oe)
  69     if (!oe)
  70         latch <= io;
  71 //assign io = oe ? ~latch : 8'bz;
  72 endmodule
  73
  74 module abc9_test012(inout io, input oe);
  75 reg latch;
  76 //always @(io or oe)
  77 //    if (!oe)
  78 //        latch <= io;
  79 assign io = oe ? ~latch : 8'bz;
  80 endmodule
  81
  82 module abc9_test013(inout [3:0] io, input oe);
  83 reg [3:0] latch;
  84 always @(io or oe)
  85     if (!oe)
  86         latch[3:0] <= io[3:0];
  87     else
  88         latch[7:4] <= io;
  89 assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
  90 assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
  91 endmodule
  92
  93 module abc9_test014(inout [7:0] io, input oe);
  94 abc9_test012_sub sub(io, oe);
  95 endmodule
  96
  97 module abc9_test012_sub(inout [7:0] io, input oe);
  98 reg [7:0] latch;
  99 always @(io or oe)
 100     if (!oe)
 101         latch[3:0] <= io;
 102     else
 103         latch[7:4] <= io;
 104 assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
 105 assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
 106 endmodule
 107
 108 module abc9_test015(input a, output b, input c);
 109 assign b = ~a;
 110 (* keep *) wire d;
 111 assign d = ~c;
 112 endmodule
 113
 114 module abc9_test016(input a, output b);
 115 assign b = ~a;
 116 (* keep *) reg c;
 117 always @* c <= ~a;
 118 endmodule
 119
 120 module abc9_test017(input a, output b);
 121 assign b = ~a;
 122 (* keep *) reg c;
 123 always @* c = b;
 124 endmodule
 125
 126 module abc9_test018(input a, output b, output c);
 127 assign b = ~a;
 128 (* keep *) wire [1:0] d;
 129 assign c = &d;
 130 endmodule
 131
 132 module abc9_test019(input a, output b);
 133 assign b = ~a;
 134 (* keep *) reg [1:0] c;
 135 reg d;
 136 always @* d <= &c;
 137 endmodule
 138
 139 module abc9_test020(input a, output b);
 140 assign b = ~a;
 141 (* keep *) reg [1:0] c;
 142 (* keep *) reg d;
 143 always @* d <= &c;
 144 endmodule
 145
 146 // Citation: https://github.com/alexforencich/verilog-ethernet
 147 module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
 148   input clk;
 149   output [47:0] m_eth_dest_mac;
 150   input m_eth_hdr_ready;
 151   output m_eth_hdr_valid;
 152   output [7:0] m_eth_payload_axis_tdata;
 153   output [7:0] m_eth_payload_axis_tdest;
 154   output [7:0] m_eth_payload_axis_tid;
 155   output m_eth_payload_axis_tkeep;
 156   output m_eth_payload_axis_tlast;
 157   input m_eth_payload_axis_tready;
 158   output m_eth_payload_axis_tuser;
 159   output m_eth_payload_axis_tvalid;
 160   output [47:0] m_eth_src_mac;
 161   output [15:0] m_eth_type;
 162   input rst;
 163   input [191:0] s_eth_dest_mac;
 164   output [3:0] s_eth_hdr_ready;
 165   input [3:0] s_eth_hdr_valid;
 166   input [31:0] s_eth_payload_axis_tdata;
 167   input [31:0] s_eth_payload_axis_tdest;
 168   input [31:0] s_eth_payload_axis_tid;
 169   input [3:0] s_eth_payload_axis_tkeep;
 170   input [3:0] s_eth_payload_axis_tlast;
 171   output [3:0] s_eth_payload_axis_tready;
 172   input [3:0] s_eth_payload_axis_tuser;
 173   input [3:0] s_eth_payload_axis_tvalid;
 174   input [191:0] s_eth_src_mac;
 175   input [63:0] s_eth_type;
 176   (* keep *)
 177   wire [0:0] grant, request;
 178   wire a;
 179   not u0 (
 180     a,
 181     grant[0]
 182   );
 183   and u1  (
 184     request[0],
 185     s_eth_hdr_valid[0],
 186     a
 187   );
 188   (* keep *)
 189   MUXF8 u2  (
 190     .I0(1'bx),
 191     .I1(1'bx),
 192     .O(o),
 193     .S(1'bx)
 194   );
 195   arbiter  arb_inst (
 196     .acknowledge(acknowledge),
 197     .clk(clk),
 198     .grant(grant),
 199     .grant_encoded(grant_encoded),
 200     .grant_valid(grant_valid),
 201     .request(request),
 202     .rst(rst)
 203   );
 204 endmodule
 205
 206 module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded);
 207   input [3:0] acknowledge;
 208   input clk;
 209   output [3:0] grant;
 210   output [1:0] grant_encoded;
 211   output grant_valid;
 212   input [3:0] request;
 213   input rst;
 214 endmodule
 215
 216 (* abc9_box, blackbox *)
 217 module MUXF8(input I0, I1, S, output O);
 218 specify
 219     (I0 => O) = 0;
 220     (I1 => O) = 0;
 221     (S => O) = 0;
 222 endspecify
 223 endmodule
 224
 225 // Citation: https://github.com/alexforencich/verilog-ethernet
 226 module abc9_test022
 227 (
 228     input  wire        clk,
 229     input  wire        i,
 230     output wire [7:0]  m_eth_payload_axis_tkeep
 231 );
 232     reg [7:0]  m_eth_payload_axis_tkeep_reg = 8'd0;
 233     assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
 234     always @(posedge clk)
 235         m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
 236 endmodule
 237
 238 // Citation: https://github.com/riscv/riscv-bitmanip
 239 module abc9_test023 #(
 240         parameter integer N = 2,
 241         parameter integer M = 2
 242 ) (
 243         input [7:0] din,
 244         output [M-1:0] dout
 245 );
 246         wire [2*M-1:0] mask = {M{1'b1}};
 247         assign dout = (mask << din[N-1:0]) >> M;
 248 endmodule
 249
 250 module abc9_test024(input [3:0] i, output [3:0] o);
 251 abc9_test024_sub a(i[1:0], o[1:0]);
 252 endmodule
 253
 254 module abc9_test024_sub(input [1:0] i, output [1:0] o);
 255 assign o = i;
 256 endmodule
 257
 258 module abc9_test025(input [3:0] i, output [3:0] o);
 259 abc9_test024_sub a(i[2:1], o[2:1]);
 260 endmodule
 261
 262 module abc9_test026(output [3:0] o, p);
 263 assign o = { 1'b1, 1'bx };
 264 assign p = { 1'b1, 1'bx, 1'b0 };
 265 endmodule
 266
 267 module abc9_test030(input [3:0] d, input en, output reg [3:0] q);
 268 always @*
 269   if (en)
 270     q <= d;
 271 endmodule
 272
 273 module abc9_test031(input clk1, clk2, d, output reg q1, q2);
 274 always @(posedge clk1) q1 <= d;
 275 always @(negedge clk2) q2 <= q1;
 276 endmodule
 277
 278 module abc9_test032(input clk, d, r, output reg q);
 279 always @(posedge clk or posedge r)
 280     if (r) q <= 1'b0;
 281     else q <= d;
 282 endmodule
 283
 284 module abc9_test033(input clk, d, r, output reg q);
 285 always @(negedge clk or posedge r)
 286     if (r) q <= 1'b1;
 287     else q <= d;
 288 endmodule
 289
 290 module abc9_test034(input clk, d, output reg q1, q2);
 291 always @(posedge clk) q1 <= d;
 292 always @(posedge clk) q2 <= q1;
 293 endmodule
 294
 295 module abc9_test035(input clk, d, output reg [1:0] q);
 296 always @(posedge clk) q[0] <= d;
 297 always @(negedge clk) q[1] <= q[0];
 298 endmodule
 299
 300 module abc9_test036(input A, B, S, output [1:0] O);
 301   (* keep *)
 302   MUXF8 m  (
 303     .I0(I0),
 304     .I1(I1),
 305     .O(O[0]),
 306     .S(S)
 307   );
 308   MUXF8 m2  (
 309     .I0(I0),
 310     .I1(I1),
 311     .O(O[1]),
 312     .S(S)
 313   );
 314 endmodule