Merge remote-tracking branch 'origin/master' into xaig
[yosys.git] / tests / simple_abc9 / abc9.v
1 module abc9_test001(input a, output o);
2 assign o = a;
3 endmodule
4
5 module abc9_test002(input [1:0] a, output o);
6 assign o = a[1];
7 endmodule
8
9 module abc9_test003(input [1:0] a, output [1:0] o);
10 assign o = a;
11 endmodule
12
13 module abc9_test004(input [1:0] a, output o);
14 assign o = ^a;
15 endmodule
16
17 module abc9_test005(input [1:0] a, output o, output p);
18 assign o = ^a;
19 assign p = ~o;
20 endmodule
21
22 module abc9_test006(input [1:0] a, output [2:0] o);
23 assign o[0] = ^a;
24 assign o[1] = ~o[0];
25 assign o[2] = o[1];
26 endmodule
27
28 module abc9_test007(input a, output o);
29 wire b, c;
30 assign c = ~a;
31 assign b = c;
32 abc9_test007_sub s(b, o);
33 endmodule
34
35 module abc9_test007_sub(input a, output b);
36 assign b = a;
37 endmodule
38
39 module abc9_test008(input a, output o);
40 wire b, c;
41 assign b = ~a;
42 assign c = b;
43 abc9_test008_sub s(b, o);
44 endmodule
45
46 module abc9_test008_sub(input a, output b);
47 assign b = ~a;
48 endmodule
49
50 module abc9_test009(inout io, input oe);
51 reg latch;
52 always @(io or oe)
53 if (!oe)
54 latch <= io;
55 assign io = oe ? ~latch : 1'bz;
56 endmodule
57
58 module abc9_test010(inout [7:0] io, input oe);
59 reg [7:0] latch;
60 always @(io or oe)
61 if (!oe)
62 latch <= io;
63 assign io = oe ? ~latch : 8'bz;
64 endmodule
65
66 module abc9_test011(inout io, input oe);
67 reg latch;
68 always @(io or oe)
69 if (!oe)
70 latch <= io;
71 //assign io = oe ? ~latch : 8'bz;
72 endmodule
73
74 module abc9_test012(inout io, input oe);
75 reg latch;
76 //always @(io or oe)
77 // if (!oe)
78 // latch <= io;
79 assign io = oe ? ~latch : 8'bz;
80 endmodule
81
82 module abc9_test013(inout [3:0] io, input oe);
83 reg [3:0] latch;
84 always @(io or oe)
85 if (!oe)
86 latch[3:0] <= io[3:0];
87 else
88 latch[7:4] <= io;
89 assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
90 assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
91 endmodule
92
93 module abc9_test014(inout [7:0] io, input oe);
94 abc9_test012_sub sub(io, oe);
95 endmodule
96
97 module abc9_test012_sub(inout [7:0] io, input oe);
98 reg [7:0] latch;
99 always @(io or oe)
100 if (!oe)
101 latch[3:0] <= io;
102 else
103 latch[7:4] <= io;
104 assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
105 assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
106 endmodule
107
108 module abc9_test015(input a, output b, input c);
109 assign b = ~a;
110 (* keep *) wire d;
111 assign d = ~c;
112 endmodule
113
114 module abc9_test016(input a, output b);
115 assign b = ~a;
116 (* keep *) reg c;
117 always @* c <= ~a;
118 endmodule
119
120 module abc9_test017(input a, output b);
121 assign b = ~a;
122 (* keep *) reg c;
123 always @* c = b;
124 endmodule
125
126 module abc9_test018(input a, output b, output c);
127 assign b = ~a;
128 (* keep *) wire [1:0] d;
129 assign c = &d;
130 endmodule
131
132 module abc9_test019(input a, output b);
133 assign b = ~a;
134 (* keep *) reg [1:0] c;
135 reg d;
136 always @* d <= &c;
137 endmodule
138
139 module abc9_test020(input a, output b);
140 assign b = ~a;
141 (* keep *) reg [1:0] c;
142 (* keep *) reg d;
143 always @* d <= &c;
144 endmodule