1 module abc9_test001(input a, output o);
5 module abc9_test002(input [1:0] a, output o);
9 module abc9_test003(input [1:0] a, output [1:0] o);
13 module abc9_test004(input [1:0] a, output o);
17 module abc9_test005(input [1:0] a, output o, output p);
22 module abc9_test006(input [1:0] a, output [2:0] o);
28 module abc9_test007(input a, output o);
32 abc9_test007_sub s(b, o);
35 module abc9_test007_sub(input a, output b);
39 module abc9_test008(input a, output o);
43 abc9_test008_sub s(b, o);
46 module abc9_test008_sub(input a, output b);
50 module abc9_test009(inout io, input oe);
55 assign io = oe ? ~latch : 1'bz;
58 module abc9_test010(inout [7:0] io, input oe);
63 assign io = oe ? ~latch : 8'bz;
66 module abc9_test011(inout io, input oe);
71 //assign io = oe ? ~latch : 8'bz;
74 module abc9_test012(inout io, input oe);
79 assign io = oe ? ~latch : 8'bz;
82 module abc9_test013(inout [3:0] io, input oe);
86 latch[3:0] <= io[3:0];
89 assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
90 assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
93 module abc9_test014(inout [7:0] io, input oe);
94 abc9_test012_sub sub(io, oe);
97 module abc9_test012_sub(inout [7:0] io, input oe);
104 assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
105 assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
108 module abc9_test015(input a, output b, input c);
114 module abc9_test016(input a, output b);
120 module abc9_test017(input a, output b);
126 module abc9_test018(input a, output b, output c);
128 (* keep *) wire [1:0] d;
132 module abc9_test019(input a, output b);
134 (* keep *) reg [1:0] c;
139 module abc9_test020(input a, output b);
141 (* keep *) reg [1:0] c;
146 // Citation: https://github.com/alexforencich/verilog-ethernet
147 module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
149 output [47:0] m_eth_dest_mac;
150 input m_eth_hdr_ready;
151 output m_eth_hdr_valid;
152 output [7:0] m_eth_payload_axis_tdata;
153 output [7:0] m_eth_payload_axis_tdest;
154 output [7:0] m_eth_payload_axis_tid;
155 output m_eth_payload_axis_tkeep;
156 output m_eth_payload_axis_tlast;
157 input m_eth_payload_axis_tready;
158 output m_eth_payload_axis_tuser;
159 output m_eth_payload_axis_tvalid;
160 output [47:0] m_eth_src_mac;
161 output [15:0] m_eth_type;
163 input [191:0] s_eth_dest_mac;
164 output [3:0] s_eth_hdr_ready;
165 input [3:0] s_eth_hdr_valid;
166 input [31:0] s_eth_payload_axis_tdata;
167 input [31:0] s_eth_payload_axis_tdest;
168 input [31:0] s_eth_payload_axis_tid;
169 input [3:0] s_eth_payload_axis_tkeep;
170 input [3:0] s_eth_payload_axis_tlast;
171 output [3:0] s_eth_payload_axis_tready;
172 input [3:0] s_eth_payload_axis_tuser;
173 input [3:0] s_eth_payload_axis_tvalid;
174 input [191:0] s_eth_src_mac;
175 input [63:0] s_eth_type;
177 wire [0:0] grant, request;
196 .acknowledge(acknowledge),
199 .grant_encoded(grant_encoded),
200 .grant_valid(grant_valid),
206 module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded);
207 input [3:0] acknowledge;
210 output [1:0] grant_encoded;
216 (* abc9_box_id=1, whitebox *)
217 module MUXF8(input I0, I1, S, output O);
220 // Citation: https://github.com/alexforencich/verilog-ethernet
225 output wire [7:0] m_eth_payload_axis_tkeep
227 reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
228 assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
229 always @(posedge clk)
230 m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
233 // Citation: https://github.com/riscv/riscv-bitmanip
234 module abc9_test023 #(
235 parameter integer N = 2,
236 parameter integer M = 2
241 wire [2*M-1:0] mask = {M{1'b1}};
242 assign dout = (mask << din[N-1:0]) >> M;
245 module abc9_test024(input [3:0] i, output [3:0] o);
246 abc9_test024_sub a(i[1:0], o[1:0]);
249 module abc9_test024_sub(input [1:0] i, output [1:0] o);
253 module abc9_test025(input [3:0] i, output [3:0] o);
254 abc9_test024_sub a(i[2:1], o[2:1]);
257 module abc9_test026(output [3:0] o, p);
258 assign o = { 1'b1, 1'bx };
259 assign p = { 1'b1, 1'bx, 1'b0 };
262 module abc9_test030(input [3:0] d, input en, output reg [3:0] q);
268 module abc9_test031(input clk1, clk2, d, output reg q1, q2);
269 always @(posedge clk1) q1 <= d;
270 always @(negedge clk2) q2 <= q1;
273 module abc9_test032(input clk, d, r, output reg q);
274 always @(posedge clk or posedge r)
279 module abc9_test033(input clk, d, r, output reg q);
280 always @(negedge clk or posedge r)
285 module abc9_test034(input clk, d, output reg q1, q2);
286 always @(posedge clk) q1 <= d;
287 always @(posedge clk) q2 <= q1;
290 module abc9_test035(input clk, d, output reg [1:0] q);
291 always @(posedge clk) q[0] <= d;
292 always @(negedge clk) q[1] <= q[0];
295 module abc9_test036(input A, B, S, output [1:0] O);