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Add ability to override verilog mode for verific -f command
[yosys.git] / tests / sva / .gitignore
1 /*_pass.sby
2 /*_fail.sby
3 /*_pass
4 /*_fail
5 /*.ok
6 /vhdlpsl[0-9][0-9]
7 /vhdlpsl[0-9][0-9].sby