1 module top (input logic clock, ctrl);
2 logic read = 0, write = 0, ready = 0;
4 always @(posedge clock) begin
10 a_rw: assert property ( @(posedge clock) !(read && write) );
12 a_wr: assert property ( @(posedge clock) write |-> ready );
14 a_wr: assert property ( @(posedge clock) write |=> ready );