tests/sva/basic01.sv

   1 module top (input logic clock, ctrl);
   2         logic read = 0, write = 0, ready = 0;
   3
   4         always @(posedge clock) begin
   5                 read <= !ctrl;
   6                 write <= ctrl;
   7                 ready <= write;
   8         end
   9
  10         a_rw: assert property ( @(posedge clock) !(read && write) );
  11 `ifdef FAIL
  12         a_wr: assert property ( @(posedge clock) write |-> ready );
  13 `else
  14         a_wr: assert property ( @(posedge clock) write |=> ready );
  15 `endif
  16 endmodule