1 module top (input logic clk, input logic selA, selB, QA, QB, output logic Q);
2 always @(posedge clk) begin
7 check_selA: assert property ( @(posedge clk) selA |=> Q == $past(QA) );
8 check_selB: assert property ( @(posedge clk) selB |=> Q == $past(QB) );
10 assume_not_11: assume property ( @(posedge clk) !(selA & selB) );