tests/sva/basic03.sv

   1 module top (input logic clk, input logic selA, selB, QA, QB, output logic Q);
   2         always @(posedge clk) begin
   3                 if (selA) Q <= QA;
   4                 if (selB) Q <= QB;
   5         end
   6
   7         check_selA: assert property ( @(posedge clk) selA |=> Q == $past(QA) );
   8         check_selB: assert property ( @(posedge clk) selB |=> Q == $past(QB) );
   9 `ifndef FAIL
  10         assume_not_11: assume property ( @(posedge clk) !(selA & selB) );
  11 `endif
  12 endmodule