tests/sva/basic04.sv

   1 module top_properties (input logic clock, read, write, ready);
   2         a_rw: assert property ( @(posedge clock) !(read && write) );
   3 `ifdef FAIL
   4         a_wr: assert property ( @(posedge clock) write |-> ready );
   5 `else
   6         a_wr: assert property ( @(posedge clock) write |=> ready );
   7 `endif
   8 endmodule
   9
  10 bind top top_properties properties_inst (.*);