1 module top_properties (input logic clock, read, write, ready);
2 a_rw: assert property ( @(posedge clock) !(read && write) );
4 a_wr: assert property ( @(posedge clock) write |-> ready );
6 a_wr: assert property ( @(posedge clock) write |=> ready );
10 bind top top_properties properties_inst (.*);