tests/sva/basic04.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity top is
   5         port (
   6                 clock : in std_logic;
   7                 ctrl : in std_logic;
   8                 x : out std_logic
   9         );
  10 end entity;
  11
  12 architecture rtl of top is
  13         signal read : std_logic := '0';
  14         signal write : std_logic := '0';
  15         signal ready : std_logic := '0';
  16 begin
  17         process (clock) begin
  18                 if (rising_edge(clock)) then
  19                         read <= not ctrl;
  20                         write <= ctrl;
  21                         ready <= write;
  22                 end if;
  23         end process;
  24
  25         x <= read xor write xor ready;
  26 end architecture;