tests/sva/basic05.sv

   1 module top (input logic clock, ctrl);
   2         logic read, write, ready;
   3
   4         demo uut (
   5                 .clock(clock),
   6                 .ctrl(ctrl)
   7         );
   8
   9         assign read = uut.read;
  10         assign write = uut.write;
  11         assign ready = uut.ready;
  12
  13         a_rw: assert property ( @(posedge clock) !(read && write) );
  14 `ifdef FAIL
  15         a_wr: assert property ( @(posedge clock) write |-> ready );
  16 `else
  17         a_wr: assert property ( @(posedge clock) write |=> ready );
  18 `endif
  19 endmodule