1 module top (input logic clock, ctrl);
2 logic read, write, ready;
9 assign read = uut.read;
10 assign write = uut.write;
11 assign ready = uut.ready;
13 a_rw: assert property ( @(posedge clock) !(read && write) );
15 a_wr: assert property ( @(posedge clock) write |-> ready );
17 a_wr: assert property ( @(posedge clock) write |=> ready );