1 module top (input clk, reset, up, down, output reg [7:0] cnt);
2 always @(posedge clk) begin
11 default clocking @(posedge clk); endclocking
12 default disable iff (reset);
14 assert property (up |=> cnt == $past(cnt) + 8'd 1);
15 assert property (up [*2] |=> cnt == $past(cnt, 2) + 8'd 2);
16 assert property (up ##1 up |=> cnt == $past(cnt, 2) + 8'd 2);
19 assume property (down |-> !up);
21 assert property (up ##1 down |=> cnt == $past(cnt, 2));
22 assert property (down |=> cnt == $past(cnt) - 8'd 1);
25 down [*n] |=> cnt == $past(cnt, n) - n;
28 assert property (down_n(8'd 3));
29 assert property (down_n(8'd 5));