Basic test for checking correct synthesis of SystemVerilog interfaces
[yosys.git] / tests / svinterfaces / runone.sh
1 #!/bin/bash
2
3
4 TESTNAME=$1
5
6 STDOUTFILE=${TESTNAME}.log_stdout
7 STDERRFILE=${TESTNAME}.log_stderr
8
9 echo "" > $STDOUTFILE
10 echo "" > $STDERRFILE
11
12 echo -n "Test: ${TESTNAME} -> "
13
14 $PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
15 $PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
16
17 rm -f a.out reference_result.txt dut_result.txt
18
19 set -e
20
21 iverilog -g2012 ${TESTNAME}_syn.v
22 iverilog -g2012 ${TESTNAME}_ref_syn.v
23
24 set +e
25
26 iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
27 ./a.out
28 mv output.txt reference_result.txt
29 iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
30 ./a.out
31 mv output.txt dut_result.txt
32
33 diff reference_result.txt dut_result.txt > ${TESTNAME}.diff
34 RET=$?
35 if [ "$RET" != "0" ] ; then
36 echo "ERROR!"
37 exit -1
38 fi
39
40 echo "ok"
41 exit 0