tests/svinterfaces/svinterface1.sv

   1
   2
   3 module TopModule(
   4     input logic clk,
   5     input logic rst,
   6     output logic [21:0] outOther,
   7     input logic [1:0] sig,
   8     input logic flip,
   9     output logic [1:0] sig_out,
  10     output logic [15:0] passThrough);
  11
  12   MyInterface #(.WIDTH(4)) MyInterfaceInstance();
  13
  14   SubModule1 u_SubModule1 (
  15     .clk(clk),
  16     .rst(rst),
  17     .u_MyInterface(MyInterfaceInstance),
  18     .outOther(outOther),
  19     .sig (sig)
  20   );
  21
  22   assign sig_out = MyInterfaceInstance.mysig_out;
  23
  24
  25   assign MyInterfaceInstance.setting = flip;
  26
  27   assign passThrough = MyInterfaceInstance.passThrough;
  28
  29 endmodule
  30
  31 interface MyInterface #(
  32   parameter WIDTH = 3)(
  33   );
  34
  35   logic setting;
  36   logic [WIDTH-1:0] other_setting;
  37
  38   logic [1:0] mysig_out;
  39
  40   logic [15:0] passThrough;
  41
  42     modport submodule1 (
  43         input  setting,
  44         output other_setting,
  45         output mysig_out,
  46         output passThrough
  47     );
  48
  49     modport submodule2 (
  50         input  setting,
  51         output other_setting,
  52         input  mysig_out,
  53         output passThrough
  54     );
  55
  56 endinterface
  57
  58
  59 module SubModule1(
  60     input logic clk,
  61     input logic rst,
  62     MyInterface.submodule1 u_MyInterface,
  63     input logic [1:0] sig,
  64     output logic [21:0] outOther
  65
  66   );
  67
  68   always_ff @(posedge clk or posedge rst)
  69     if(rst)
  70       u_MyInterface.mysig_out <= 0;
  71     else begin
  72       if(u_MyInterface.setting)
  73         u_MyInterface.mysig_out <= sig;
  74       else
  75         u_MyInterface.mysig_out <= ~sig;
  76     end
  77
  78   MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
  79
  80   SubModule2 u_SubModule2 (
  81     .clk(clk),
  82     .rst(rst),
  83     .u_MyInterfaceInSub2(u_MyInterface),
  84     .u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
  85   );
  86
  87     assign outOther = MyInterfaceInstanceInSub.other_setting;
  88
  89     assign MyInterfaceInstanceInSub.setting = 0;
  90     assign MyInterfaceInstanceInSub.mysig_out = sig;
  91
  92 endmodule
  93
  94 module SubModule2(
  95
  96     input logic clk,
  97     input logic rst,
  98     MyInterface.submodule2 u_MyInterfaceInSub2,
  99     MyInterface.submodule2 u_MyInterfaceInSub3
 100
 101   );
 102
 103    always_comb begin
 104       if (u_MyInterfaceInSub3.mysig_out == 2'b00)
 105         u_MyInterfaceInSub3.other_setting[21:0] = 1000;
 106       else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
 107         u_MyInterfaceInSub3.other_setting[21:0] = 2000;
 108       else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
 109         u_MyInterfaceInSub3.other_setting[21:0] = 3000;
 110       else
 111         u_MyInterfaceInSub3.other_setting[21:0] = 4000;
 112    end
 113
 114     assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
 115     assign u_MyInterfaceInSub2.passThrough[15:8] = 200;
 116
 117 endmodule