Merge remote-tracking branch 'origin/master' into xc7mux
[yosys.git] / tests / svinterfaces / svinterface1_ref.v
1
2 module TopModule(
3 input logic clk,
4 input logic rst,
5 input logic [1:0] sig,
6 input logic flip,
7 output logic [15:0] passThrough,
8 output logic [21:0] outOther,
9 output logic [1:0] sig_out);
10
11
12 logic MyInterfaceInstance_setting;
13 logic [3:0] MyInterfaceInstance_other_setting;
14 logic [1:0] MyInterfaceInstance_mysig_out;
15
16 SubModule1 u_SubModule1 (
17 .clk(clk),
18 .rst(rst),
19 .u_MyInterface_setting(MyInterfaceInstance_setting),
20 .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
21 .u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
22 .outOther(outOther),
23 .passThrough (passThrough),
24 .sig (sig)
25 );
26
27 assign sig_out = MyInterfaceInstance_mysig_out;
28
29
30 assign MyInterfaceInstance_setting = flip;
31
32 endmodule
33
34
35 module SubModule1(
36 input logic clk,
37 input logic rst,
38 input logic u_MyInterface_setting,
39 output logic [3:0] u_MyInterface_other_setting,
40 output logic [1:0] u_MyInterface_mysig_out,
41 output logic [21:0] outOther,
42 input logic [1:0] sig,
43 output logic [15:0] passThrough
44 );
45
46 always @(posedge clk or posedge rst)
47 if(rst)
48 u_MyInterface_mysig_out <= 0;
49 else begin
50 if(u_MyInterface_setting)
51 u_MyInterface_mysig_out <= sig;
52 else
53 u_MyInterface_mysig_out <= ~sig;
54 end
55
56 logic MyInterfaceInstanceInSub_setting;
57 logic [21:0] MyInterfaceInstanceInSub_other_setting;
58 logic [1:0] MyInterfaceInstanceInSub_mysig_out;
59
60
61 SubModule2 u_SubModule2 (
62 .clk(clk),
63 .rst(rst),
64 .u_MyInterfaceInSub2_setting(u_MyInterface_setting),
65 .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
66 .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
67 .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
68 .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
69 .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
70 .passThrough (passThrough)
71 );
72 assign outOther = MyInterfaceInstanceInSub_other_setting;
73
74 assign MyInterfaceInstanceInSub_setting = 0;
75 assign MyInterfaceInstanceInSub_mysig_out = sig;
76
77 endmodule
78
79 module SubModule2(
80
81 input logic clk,
82 input logic rst,
83 input logic u_MyInterfaceInSub2_setting,
84 output logic [3:0] u_MyInterfaceInSub2_other_setting,
85 input logic [1:0] u_MyInterfaceInSub2_mysig_out,
86 input logic u_MyInterfaceInSub3_setting,
87 output logic [21:0] u_MyInterfaceInSub3_other_setting,
88 input logic [1:0] u_MyInterfaceInSub3_mysig_out,
89 output logic [15:0] passThrough
90
91 );
92
93 always @(u_MyInterfaceInSub3_mysig_out) begin
94 if (u_MyInterfaceInSub3_mysig_out == 2'b00)
95 u_MyInterfaceInSub3_other_setting[21:0] = 1000;
96 else if (u_MyInterfaceInSub3_mysig_out == 2'b01)
97 u_MyInterfaceInSub3_other_setting[21:0] = 2000;
98 else if (u_MyInterfaceInSub3_mysig_out == 2'b10)
99 u_MyInterfaceInSub3_other_setting[21:0] = 3000;
100 else
101 u_MyInterfaceInSub3_other_setting[21:0] = 4000;
102 end
103
104 assign passThrough[7:0] = 124;
105 assign passThrough[15:8] = 200;
106
107 endmodule